Exemplary embodiments relate to a nonvolatile memory device and, more particularly, to a nonvolatile memory device which is capable of improving the degree of integration.
FIG. 1 shows the configuration of a known nonvolatile memory device.
Referring to FIG. 1, the nonvolatile memory device includes a normal memory cell array 11, a page buffer unit 12, a normal column decoder 13, a normal pre-decoder 14, a redundancy memory cell array 21, a redundancy page buffer unit 22, a redundancy column decoder 23, and a redundancy pre-decoder 24.
The known nonvolatile memory device includes a number of I/O lines IO<n−1:0> coupled to the normal column decoder 13 and a number of redundancy I/O lines RIO<k−1:0> coupled to the redundancy column decoder 23. Furthermore, the normal column decoder 13 includes a number of decoders CD<n−1:0> corresponding to the respective I/O lines IO<n−1:0> and performs a column address decoding operation on each of the I/O lines. The redundancy column decoder 23 has the same construction as the normal column decoder 13.
The known nonvolatile memory device has to send column address decoding signals CS<m−1:0> to respective page buffers (not shown) included in each page buffer group (for example, PBG<0>). Accordingly, the nonvolatile memory device includes lots of lines for sending signals. As the degree of integration of chips increases, it becomes increasing difficult to arrange the page buffers and the column decoders in the margin between bit lines.
Furthermore, the column address decoding signals CS<m−1:0> for selecting a specific page buffer are sent to the specific page buffer through transistors driven in response to pre-decoding signals a, b, and c outputted by the normal pre-decoder 14. The column address decoding signals increase resistance of a corresponding I/O line and serve as a factor to delay the transmission speed of data, stored in the page buffer, to the I/O line, thereby reducing the operating speed.
Furthermore, the nonvolatile memory device further requires a column address repair circuit unit and a circuit unit for controlling redundancy I/O lines in order to perform a column repair operation on a fail column. Accordingly, there is concern with respect to the area of the known nonvolatile memory device.